1. Field of the Invention
The present invention relates to a reset circuit, and more specifically to a reset circuit for a flipflop.
2. Description of Related Art
In the prior art, this type of reset circuit has been used in a processor having a data bus, in order to prevent a pass-through current occurring due to a logic collision on a bus caused because the output value of bus controlling flipflops are indefinite at a power-on time.
Referring to FIG. 6, there is shown a block diagram of one example of the prior art reset circuit. In the shown prior art example shown in FIG. 6, a plurality of data path blocks 1, 2 and 3 are connected to the same bus 16, which is connected with a bus latch 32. These data path blocks are the same in a connection fashion with the bus and in an internal construction. Therefore, the data path block 3 will be described in detail.
In the data path block 3, a data path unit 6 has data output terminals connected to tristate buffers 14 and 15, respectively, and data input terminals connected to the data bus 16. The tristate buffers are of the same number as a bit width of the data bus 16. Here, it is assumed that the bit width of the data bus 16 is 2 for simplification of description and drawings. An output of the tristate buffers is connected to the data bus 16. A control terminal of the tristate buffers 14 and 15 is connected to an output of a flipflop circuit (abbreviated to "FF" in the drawings) 31. A data input terminal of the flipflop 31 is connected to one corresponding signal line of selection signal lines 17, and a clock terminal of the flipflop 31 is connected to a clock signal line 20. A reset terminal of the flipflop 31 is connected to a reset signal line 25. A control circuit 19 has output terminals of the number corresponding to the number of data path blocks connected to the bus. The output terminals of the control circuit 19 are connected to the selection signal lines 17, respectively. The reset signal line 25 is connected to an output of a power-on-reset circuit 23.
Now, an operation of the prior art reset circuit will be described. In the circuit shown in FIG. 6, when it is powered on, the content held in the flipflops associated to the respective units become indefinite. Therefore, assuming that the flipflops had no reset input, there is a possibility that for example, the output of the flipflop 30 becomes a high level, the output of the flipflop 31 becomes a high level, an output of a tristate buffer 13 becomes a high level, and the output of the tristate buffer 14 becomes a low level, with the result that a pass-through current flows through the bus. However, since the reset terminal of each flipflop is supplied with the power-on-reset signal, each flipflop is reset at the power-on time, so that the output of each flipflop becomes "0", with the result that the output of all the tristates buffers connected to the bus have a high impedance, and therefore, the bus is held at the value of the bus latch 32 Furthermore, if the external clock is inputted, the value of each flipflop becomes a value reflecting the corresponding output of the control circuit 19, so that the bus is driven with only one unit.
The above mentioned prior art reset circuit has a problem in which the flipflop having the reset function, of the number equal to the number of the units, are required, and in addition, it is necessary to lay out the reset signal line. This results in an increased circuit scale, and in an increased occupying area when the, circuit is incorporated in an LSI (large scale integrated circuit.